The present invention relates to a data processing apparatus having a function to prefetch instructions and, more particularly, to a microprocessor of such an apparatus.
FIG. 3 is a block diagram of a conventional microprocessor having a function to prefetch instructions. In FIG. 3, reference numeral 1 denotes an instruction queue, 2 denotes an operation decoder, and 3 denotes an instruction execution unit.
The operation of the microprocessor in FIG. 3 will now be described. In the microprocessor, the time for accessing the main memory is extremely longer than the time for accessing the data stored in the processor. In the case of accessing the main memory every time an instruction is fetched, the effective speed will not rise even if the operation speed of microprocessor is increased. To improve this drawback, in the microprocessor in FIG. 3, instructions are previously stored into the instruction queue 1 by useing the time when the main memory is not accessed, the instruction to be executed next is fetched into the operation decoder 2 from the instruction queue 1, thereby raising the effective speed of the microprocessor. However, after a certain series of instructions were executed, when the operation decoder 2 issues a request to fetch the instructions to the instruction queue 1, if the instruction queue 1 is empty, the instruction to be executed next must be directly fetched into the instruction queue 1 from the main memory.
As described above, the conventional data processing apparatus having the instruction prefetching function has such a problem that when the instruction queue 1 is empty, the execution of instructions must be interrupted for the period of time until the instruction to be executed next is directly fetched from the main memory, so that the executing speed is decreased.